1. Field of the Invention
The present invention relates to power supply to a gate electrode of a vertical MOS transistor and, more particularly, to a semiconductor device having a structure suitable for power supply to a gate electrode shared between a plurality of vertical MOS transistors.
2. Description of Related Art
A conventional three-dimensional transistor, i.e., a vertical MOS transistor, has a structure wherein: in an Si pillar forming source/drain diffusion layers and a channel, the channel portion is surrounded by a gate insulating film and a gate electrode, while the source/drain diffusion layers are formed at top and bottom of the silicon pillar to sandwich the channel portion completely, as shown in FIG. 2 of United States Patent US2004/26281A1 (Document 1).
Japanese Patent Laid-Open No. 2002-94027 (Document 2) discloses a semiconductor memory device having a plurality of silicon pillars defined by a lattice-shaped trench formed in a surface of a silicon substrate, wherein: a select transistor is formed on a side surface of each silicon pillar with its source or drain diffusion layer formed in the bottom of the trench, the select transistor forming a select transistor of a one-transistor one-capacitor type DRAM cell; and the trench bottom diffusion layer is connected to a fixed voltage common to a multiplicity of memory cells. This document also discloses the technique of continuously interconnecting gate electrodes each formed so as to come into contact with one side surface of a respective one of the silicon pillars across an intervening gate insulating film, to form a word line.
Document 1 does not make any explicit mention of a structure for potential supply to the gate electrode of the vertical MOS transistor. Nor does Document 1 disclose a structure for power supply to a gate electrode shared between a plurality of vertical MOS transistors.
Normally, it is supposed that the potential supply is effected through a contact formed at any point on the gate electrode material. However, it is not easy to form the contact directly on the gate electrode material in an array section densely formed with minute vertical MOS transistors. Even if the formation of the contact is possible, there arises another problem that the contact position is limited and, hence, the design freedom is limited.
The semiconductor device disclosed in Document 2 involves a problem that since the channel is formed in only one side surface of each silicon pillar, the semiconductor device is inferior in subthreshold properties to the vertical MOS transistor described in Document 1 in which the periphery of the channel is covered with the gate electrode so as to be completely depleted.
Accordingly, a demand exists for a semiconductor device including means having a high degree of design freedom for potential supply to a gate electrode in an array section densely formed with vertical MOS transistors.